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s6b 0718 104 seg / 81 com drive r & controller for stn lcd feb . 2000 . ver. 2. 1 prepared by: hyoung-seok lee lhs98@samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
104 seg / 81 com driver & controller for stn lcd S6B0718 2 S6B0718 specification revision history version content date 0.0 original nov.1998 0.1 modify syntax errors append n-line inversion wave form to figure 1 1 on page 1 9 . modify figure 1 2 on page 2 0 dec. 1998 1.0 change the number of com/seg (85com / 100seg -> 81com / 104seg) modify pad location mar. 199 9 1.1 append pad center coordinates to t able 1, 2 on page 4, 5 append referential instruction setup flow on page 48 to 51 apr. 199 9 1.2 change bumped pad size (m odify f igure 2 and t able 1 on page 3) change the pad center coordinates of com39 and coms1. ( m odify t able 2 on page 4) change lcd power supply voltage ( m odify v out and v 0 v oltage on page1, 52, 53, 54, 55) may. 199 9 1.3 modify set partial display duty ratio (refer to page 32) modify n-line inversion register ? 2 to 32 ? -> ? 3 to 3 3 ? (refer to page 41) change consumption current ? 2ma ? -> ? 2ua ? , ? 10ma ? -> ? 10ua ? (refer to page 47) add partial duty changing ? waiting for discharging the lcd power levels (refer to figure 39) jun.1999 1.4 fix the tbd value of dc/ac characteristics. aug.1999 1.4 remove n-line inversion function. oct. 1999 2.0 change the supply voltage(vdd) range (2.4 to 5.5 -> 2.4 to 3.6) nov. 1999 2.0 repair the cog/ilb align key coordinate. dec. 1999 2.1 change sales/product code to integration code (ks0718 -> S6B0718) feb. 2000
S6B0718 104 seg / 81 com driver & controller for stn lcd 3 co ntents introduction ................................ ................................ ................................ ................................ .................. 1 block diagram ................................ ................................ ................................ ................................ ............... 2 pad configuration ................................ ................................ ................................ ................................ ....... 3 pad center coordinates ................................ ................................ ................................ ............................ 5 pin description ................................ ................................ ................................ ................................ .............. 7 power supply ................................ ................................ ................................ ................................ .......... 7 lcd driver supply ................................ ................................ ................................ ................................ .. 7 system control ................................ ................................ ................................ ................................ ..... 8 microprocessor interface ................................ ................................ ................................ ............... 9 lcd driver outputs ................................ ................................ ................................ ............................. 11 functional description ................................ ................................ ................................ ............................ 12 microprocessor interface ................................ ................................ ................................ ............. 12 display data ram (ddram) ................................ ................................ ................................ .................. 15 lcd display circuits ................................ ................................ ................................ ............................ 19 lcd driver circuit ................................ ................................ ................................ ............................... 21 power supply circuits ................................ ................................ ................................ ...................... 24 referece circuit examples ................................ ................................ ................................ .............. 29 reset circuit ................................ ................................ ................................ ................................ ......... 31 instruction description ................................ ................................ ................................ ........................... 32 specifications ................................ ................................ ................................ ................................ .............. 51 absolute maximum ratings ................................ ................................ ................................ ............... 51 dc characteristics ................................ ................................ ................................ ............................. 52 ac characteristics ................................ ................................ ................................ ............................. 55 reference applications ................................ ................................ ................................ ........................... 59 microprocessor interface ................................ ................................ ................................ ............. 59 connections between S6B0718 and lcd panel ................................ ................................ ............ 60
S6B0718 104 seg / 81 com driver & controller for stn lcd 1 introduction the S6B0718 is a driver & controller lsi for graphic dot-matrix liquid crystal display systems. it contains 81 common and 104 segment driver circuits. this chip is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip display data ram of 89 x 104 bits. it provides a highly flexible display section due to 1-to-1 correspondence between on-chip display data ram bits and lcd panel pixels. and it performs display data ram read/write operation with no external ly operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. features driver output circuits - 81 common outputs / 104 segment outputs applicable duty ratios programmable duty ratio applicable lcd bias maximum display area 1/9 to 1/81 1/4 to 1/11 81 104 - various partial display - partial window moving & data scrolling on-chip display data ram - capacity: 89 x 104 = 9,256 bits - bit data "1": a dot of display is illuminated . - bit data "0": a dot of display is not illuminated . microprocessor interface - 8-bit parallel bi-directional interface with 6800-series or 8080-series - serial interface (only write operation) available on-chip low power analog circuit - on-chip oscillator circuit - voltage converter (x3, x4, x5 or x6) - voltage regulator (temperature coefficient: -0.05%/ c or external input) - on-chip electronic contrast control function (64 steps) - voltage follower (lcd bias: 1/4 to 1/11) operating voltage range - supply voltage ( v dd ): 2.4 to 3.6 v - lcd driving voltage (v lcd = v0 - v ss ): 4.0 to 1 5 .0 v low power consumption - 150 m a max . (v dd = 3v, x 5 boosting, v0 = 1 2 v, i nternal power supply on and display off) - 15 m a max. (during power save [standby] mode) package type - gold bumped chip or tcp
104 seg / 81 com driver & controller for stn lcd S6B0718 2 block diagram internal p ower supply ms cl sync m frs fr vdd v0 v1 v2 v3 v4 vss hpmb v0 vr intrs vext ref vout c1- c1+ c2- c2+ c3+ c4+ c5+ vci v / c circuit v / r c ircuit v / f circuit 8 2 common driver circuits mpu interface (parallel & serial) instruction decoder & register status register bus holder column address circuit line address circuit page address circuit display data ram 89 x 104 = 9,256 bits segment controller static driver display timing generator circuit common controller db0 db1 db2 db3 db4 db5 db6(sclk) db7(sid) rw_wr e_rd rs cs2 cs1b ps c68 resetb coms 1 com 79 : : : com0 coms seg 103 seg102 seg101 : : seg2 seg1 seg0 oscillator 104 segment d river circuits figure 1 . block diagram
S6B0718 104 seg / 81 com driver & controller for stn lcd 3 pad configuration 80 y 113 242 112 243 81 274 1 s6b 0718 (top view , pads up ) (0,0) x ee eeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeee ee eeeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeeeeee eeee - - - - eee e eeee - - - - eee e figure 2 . S6B0718 chip configuration table 1 . S6B0718 pad dimensions size item pad no. x y unit chip size - 8350 2380 1 to 80 90 82 to 110 115 to 240 245 to 273 60 81 111 to 114 241 to 244 pad pitch 274 80 1 to 80 54 112 81 110 80 82 to 110 110 40 111 to 112 110 60 113 to 114 60 110 115 to 240 40 110 241 to 242 60 110 243 to 244 110 60 245 to 273 110 40 b umped pad size (max.) 274 110 80 b umped pad height a ll pad 14 (typ.) m m
104 seg / 81 com driver & controller for stn lcd S6B0718 4 cog align key coordinate ilb align key coordinate 30 m m 30 m m 30 m m (+ 3565 , +640 ) 30 m m 30 m m 30 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m (- 3493.5 , + 488.5 ) (+ 3493. 5, -4 08. 5)
S6B0718 104 seg / 81 com driver & controller for stn lcd 5 pad center coordinates table 2 . p ad center coordinates [unit: m m] no. name x y no. name x y no. name x y 1 frs -3555 -1066 51 c3+ 945 -1066 101 com19 4028 190 2 fr -3465 -1066 52 c3+ 1035 -1066 102 com18 4028 250 3 test1 -3375 -1066 53 c1- 1125 -1066 103 com17 4028 310 4 test2 -3285 -1066 54 c1- 1215 -1066 104 com16 4028 370 5 test3 -3195 -1066 55 c1+ 1305 -1066 105 com15 4028 430 6 cl -3105 -1066 56 c1+ 1395 -1066 106 com14 4028 490 7 m -3015 -1066 57 c2+ 1485 -1066 107 com13 4028 550 8 sync -2925 -1066 58 c2+ 1575 -1066 108 com12 4028 610 9 vss -2835 -1066 59 c2- 1665 -1066 109 com11 4028 670 10 hpmb -2745 -1066 60 c2- 1755 -1066 110 com10 4028 730 11 ms -2655 -1066 61 c4+ 1845 -1066 111 dummy 4028 810 12 vdd -2565 -1066 62 c4+ 1935 -1066 112 dummy 4028 890 13 ps -2475 -1066 63 vss 2025 -1066 113 dummy 3910 1043 14 c68 -2385 -1066 64 ref 2115 -1066 114 dummy 3830 1043 15 vss -2295 -1066 65 vext 2205 -1066 115 com9 3750 1043 16 cs1b -2205 -1066 66 vdd 2295 -1066 116 com8 3690 1043 17 cs2 -2115 -1066 67 intrs 2385 -1066 117 com7 3630 1043 18 vdd -2025 -1066 68 vss 2475 -1066 118 com6 3570 1043 19 resetb -1935 -1066 69 v4 2565 -1066 119 com5 3510 1043 20 rs -1845 -1066 70 v4 2655 -1066 120 com4 3450 1043 21 vss -1755 -1066 71 v3 2745 -1066 121 com3 3390 1043 22 rw_wr -1665 -1066 72 v3 2835 -1066 122 com2 3330 1043 23 e_rd -1575 -1066 73 v2 2925 -1066 123 com1 3270 1043 24 vdd -1485 -1066 74 v2 3015 -1066 124 com0 3210 1043 25 db0 -1395 -1066 75 v1 3105 -1066 125 coms 3150 1043 26 db1 -1305 -1066 76 v1 3195 -1066 126 seg0 3090 1043 27 db2 -1215 -1066 77 v0 3285 -1066 127 seg1 3030 1043 28 db3 -1125 -1066 78 v0 3375 -1066 128 seg2 2970 1043 29 db4 -1035 -1066 79 vr 3465 -1066 129 seg3 2910 1043 30 db5 -945 -1066 80 vr 3555 -1066 130 seg4 2850 1043 31 db6 -855 -1066 81 com39 4028 -1030 131 seg5 2790 1043 32 db7 -765 -1066 82 com38 4028 -950 132 seg6 2730 1043 33 vdd -675 -1066 83 com37 4028 -890 133 seg7 2670 1043 34 vdd -585 -1066 84 com36 4028 -830 134 seg8 2610 1043 35 vdd -495 -1066 85 com35 4028 -770 135 seg9 2550 1043 36 vdd -405 -1066 86 com34 4028 -710 136 seg10 2490 1043 37 vdd -315 -1066 87 com33 4028 -650 137 seg11 2430 1043 38 vci -225 -1066 88 com32 4028 -590 138 seg12 2370 1043 39 vci -135 -1066 89 com31 4028 -530 139 seg13 2310 1043 40 vss -45 -1066 90 com30 4028 -470 140 seg14 2250 1043 41 vss 45 -1066 91 com29 4028 -410 141 seg15 2190 1043 42 vss 135 -1066 92 com28 4028 -350 142 seg16 2130 1043 43 vss 225 -1066 93 com27 4028 -290 143 seg17 2070 1043 44 vss 315 -1066 94 com26 4028 -230 144 seg18 2010 1043 45 vout 405 -1066 95 com25 4028 -170 145 seg19 1950 1043 46 vout 495 -1066 96 com24 4028 -110 146 seg20 1890 1043 47 vout 585 -1066 97 com23 4028 -50 147 seg21 1830 1043 48 vout 675 -1066 98 com22 4028 10 148 seg22 1770 1043 49 c5+ 765 -1066 99 com21 4028 70 149 seg23 1710 1043 50 c5+ 855 -1066 100 com20 4028 130 150 seg24 1650 1043
104 seg / 81 com driver & controller for stn lcd S6B0718 6 table 2 . p ad center coordinates (continued) [ u nit: m m] no. name x y no. name x y no. name x y 151 seg25 1590 1043 201 seg75 -1410 1043 251 com57 -4028 370 152 seg26 1530 1043 202 seg76 -1470 1043 252 com58 -4028 310 153 seg27 1470 1043 203 seg77 -1530 1043 253 com59 -4028 250 154 seg28 1410 1043 204 seg78 -1590 1043 254 com60 -4028 190 155 seg29 1350 1043 205 seg79 -1650 1043 255 com61 -4028 130 156 seg30 1290 1043 206 seg80 -1710 1043 256 com62 -4028 70 157 seg31 1230 1043 207 seg81 -1770 1043 257 com63 -4028 10 158 seg32 1170 1043 208 seg82 -1830 1043 258 com64 -4028 -50 159 seg33 1110 1043 209 seg83 -1890 1043 259 com65 -4028 -110 160 seg34 1050 1043 210 seg84 -1950 1043 260 com66 -4028 -170 161 seg35 990 1043 211 seg85 -2010 1043 261 com67 -4028 -230 162 seg36 930 1043 212 seg86 -2070 1043 262 com68 -4028 -290 163 seg37 870 1043 213 seg87 -2130 1043 263 com69 -4028 -350 164 seg38 810 1043 214 seg88 -2190 1043 264 com70 -4028 -410 165 seg39 750 1043 215 seg89 -2250 1043 265 com71 -4028 -470 166 seg40 690 1043 216 seg90 -2310 1043 266 com72 -4028 -530 167 seg41 630 1043 217 seg91 -2370 1043 267 com73 -4028 -590 168 seg42 570 1043 218 seg92 -2430 1043 268 com74 -4028 -650 169 seg43 510 1043 219 seg93 -2490 1043 269 com75 -4028 -710 170 seg44 450 1043 220 seg94 -2550 1043 270 com76 -4028 -770 171 seg45 390 1043 221 seg95 -2610 1043 271 com77 -4028 -830 172 seg46 330 1043 222 seg96 -2670 1043 272 com78 -4028 -890 173 seg47 270 1043 223 seg97 -2730 1043 273 com79 -4028 -950 174 seg48 210 1043 224 seg98 -2790 1043 274 coms1 -4028 -1030 175 seg49 150 1043 225 seg99 -2850 1043 176 seg50 90 1043 226 seg100 -2910 1043 177 seg51 30 1043 227 seg101 -2970 1043 178 seg52 -30 1043 228 seg102 -3030 1043 179 seg53 -90 1043 229 seg103 -3090 1043 180 seg54 -150 1043 230 com40 -3150 1043 181 seg55 -210 1043 231 com41 -3210 1043 182 seg56 -270 1043 232 com42 -3270 1043 183 seg57 -330 1043 233 com43 -3330 1043 184 seg58 -390 1043 234 com44 -3390 1043 185 seg59 -450 1043 235 com45 -3450 1043 186 seg60 -510 1043 236 com46 -3510 1043 187 seg61 -570 1043 237 com47 -3570 1043 188 seg62 -630 1043 238 com48 -3630 1043 189 seg63 -690 1043 239 com49 -3690 1043 190 seg64 -750 1043 240 com50 -3750 1043 191 seg65 -810 1043 241 dummy -3830 1043 192 seg66 -870 1043 242 dummy -3910 1043 193 seg67 -930 1043 243 dummy -4028 890 194 seg68 -990 1043 244 dummy -4028 810 195 seg69 -1050 1043 245 com51 -4028 730 196 seg70 -1110 1043 246 com52 -4028 670 197 seg71 -1170 1043 247 com53 -4028 610 198 seg72 -1230 1043 248 com54 -4028 550 199 seg73 -1290 1043 249 com55 -4028 490 200 seg74 -1350 1043 250 com56 -4028 430
S6B0718 104 seg / 81 com driver & controller for stn lcd 7 pin description power supply table 3 . power supply p ins name i/o description vdd supply power supply v ss supply ground lcd driver suppl ies voltages the voltage determined by lcd pixel is impedance converted by an operational amplifier for application. voltages should have the following relation ship ; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the internal power circuit is active, these voltages are generated as following table according to the state of lcd b ias. lcd bias v1 v2 v3 v4 1/n bias (n-1) / n x v0 (n-2) / n x v0 ( 2/n ) x v0 ( 1/n ) x v0 v0 v1 v2 v3 v4 i/o note: n = 4 to 11 lcd driver supply table 4 . lcd driver supply p ins name i/o description c1- o capacitor 1 negative connection pin for voltage converter c1+ o capacitor 1 positive connection pin for voltage converter c2- o capacitor 2 negative connection pin for voltage converter c2+ o capacitor 2 positive connection pin for voltage converter c3+ o capacitor 3 positive connection pin for voltage converter c4+ o capacitor 4 positive connection pin for voltage converter c5+ o capacitor 5 positive connection pin for voltage converter vout i/o voltage converter input / output pin vci i voltage converter input voltage pin voltages should have the following relationship: vdd vci v0 vr i v0 voltage adjustment pin it is valid only when on-chip resistors are not used (intrs = "l") ref i selects the external vref voltage via vext pin - ref = "l": using the external vref - ref = "h": using the internal vref vext i externally input reference voltage (vref) for the internal voltage regulator it is valid only when ref is "l".
104 seg / 81 com driver & controller for stn lcd S6B0718 8 system control table 5 . system control p ins name i/o description master / slave operations select pin - ms = "h": master operation - ms = "l": slave operation the following table depends on the ms status . internal analog circuits display timing signals ms oscillator power supply cl sync m h enabled enabled output output output l disabled disabled input input input ms i cl i/o display clock input / output pin when the S6B0718 is used in master/slave mode ( m ulti - chip), the cl pins must be connected each other . sync i/o display sync input / output pin when the S6B0718 is used in master/slave mode ( m ulti-chip), the sync pins must be connected each other . m i/o lcd ac signals input / output pin when the S6B0718 is used in master/slave mode ( m ulti-chip), the m pins must be connected each other. fr o static driver common output pin this pin is used together with the frs pin. frs o static driver segment output pin this pin is used together with the fr pin. intrs i internal resistors select pin this pin selects the resistors for adjusting v0 voltage level. - intrs = "h": use the internal resistors - intrs = "l": use the external resistors vr pin and external resistive divider control v0 voltage . hpmb i power control pin of the power supplies circuit for lcd driver - hpmb = "l": high power mode - hpmb = "h": normal mode this pin is valid in master operation. test1 to test3 i test pins don ? t use these pins.
S6B0718 104 seg / 81 com driver & controller for stn lcd 9 microprocessor interface table 6 . microprocessor i nterface p ins name i/o description resetb i reset the input pin when resetb is "l", initialization is executed. parallel/serial data input select input ps interface mode data/ instruction data read / write serial clock h parallel rs db0 to db7 e_rd rw_wr - l serial rs sid(db7) write only sclk(db6) ps i *note: when ps is "l", db0 to db5 are high impedance and e_rd and rw_wr must be fixed to either "h" or "l". c68 i microprocessor interface select input pin - c68 = "h": 6800-series mpu interface - c68 = "l": 8080-series mpu interface cs1b cs2 i chip select input pins data/instruction i/o is enabled only when cs1b is "l" and cs2 is "h". when chip select is non-active, db0 to db7 may be high impedance. rs i register select input pin - rs = "h": db0 to db7 are display dat a - rs = "l": db0 to db7 are control data read / write execution control pin c68 mpu type rw_wr description h 6800-series rw read/write control input pin - rw = "h": r ead - rw = "l": w rite l 8080-series /wr write enable clock input pin the data on db0 to db7 are latched at the rising edge of the /wr signal. rw_wr i
104 seg / 81 com driver & controller for stn lcd S6B0718 10 table 6 (continued) name i/o description read / write execution control pin c68 mpu type e_rd description h 6800-series e read/write control input pin - rw = "h": when e is "h", db0 to db7 are in an output status. - rw = "l": the data on db0 to db7 are latched at the falling edge of the e signal. l 8080-series /rd read enable clock input pin when /rd is "l", db0 to db7 are in an output status. e_rd i db0 to db7 i/o 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when the serial interface selected (ps = "l"); - db0 to db5: high impedance - db6: serial input clock (sclk) - db7: serial input data (sid) when chip select is not active, db0 to db7 may be high impedance.
S6B0718 104 seg / 81 com driver & controller for stn lcd 11 lcd driver outputs table 7 . lcd d river o utputs p ins name i/o description lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m normal display reverse display h h v0 v2 h l v ss v3 l h v2 v0 l l v3 v ss power save mode v ss v ss seg0 to seg103 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m common driver output voltage h h v ss h l v0 l h v1 l l v4 power save mode v ss com0 to com79 o coms (coms1) o common output for the icons the output signals of two pins are same. when not used, these pins should be left open. note: dummy ? these pins should be opened (floated).
104 seg / 81 com driver & controller for stn lcd S6B0718 12 functional description microprocessor interface chip select input there are cs1b and cs2 pins for chip selection. the S6B0718 can interface with an mpu only when cs1b is "l" and cs2 is "h". when these pins are set to any other combination, rs, e_rd, and rw_wr inputs are disabled and db0 to db7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface S6B0718 has three types of interface with an mpu, which are one serial and two parallel interface. this parallel or serial interface is determined by ps pin as shown in table 8 table 8 . parallel / serial interface mode ps type cs1b cs2 c68 interface mode h 6800-series mpu mode h parallel cs1b cs2 l 8080-series mpu mode l serial cs1b cs2 * serial-mode * : don't care parallel interface (ps = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by c68 as shown in table 9 . the type of data transfer is determined by signals at rs, e_rd and rw_wr as shown in table 10 . table 9 . microprocessor selection for parallel interface c68 cs1b cs2 rs e_rd rw_wr db0 to db7 mpu bus h cs1b cs2 rs e rw db0 to db7 6800-series l cs1b cs2 rs /rd /wr db0 to db7 8080-series table 10 . parallel data transfer common 6800-series 8080-series description rs e_rd (e) rw_wr (rw) e_rd (/rd) rw_wr (/wr) h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction)
S6B0718 104 seg / 81 com driver & controller for stn lcd 13 serial interface (ps = "l") when the S6B0718 is active, serial data (db7) and serial clock (db6) inputs are enabled. and not active, the internal 8-bit shift register and the 3-bit counter are reset. serial data can be read on the rising edge of serial clock going into db6 and processed as 8-bit parallel data on the eighth serial clock. serial data input is display data when rs is high and control data when rs is low. since the clock signal ( db6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. cs1b cs2 sid sclk rs db6 db7 db0 db1 db2 db3 db4 db5 db6 db7 figure 3 . serial interface timing busy flag the b usy f lag indicates whether the S6B0718 is operating or not. when db7 is "h" in read status operation, this device is in busy status and will accept only read status instruction. if the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance.
104 seg / 81 com driver & controller for stn lcd S6B0718 14 data transfer the S6B0718 uses bus holder and internal data bus for d ata t ransfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 4 . and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 5 . this means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. t herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. rs /wr db0 to db7 n d(n) d(n+1) d(n+2) d(n+3) internal signals mpu signals /wr bus holder column address n n+1 n+2 n+3 n d(n) d(n+1) d(n+2) d(n+3) figure 4 . write timing rs /wr /rd db0 to db7 n mpu signals dummy d(n) d(n+1) internal signals /wr /rd bus holder column address n d(n) d(n+1) d(n+2) n n+1 n+2 n+3 figure 5 . read timing
S6B0718 104 seg / 81 com driver & controller for stn lcd 15 display data ram (ddram) the display data ram stores pixel data for the lcd. it is 89-row by 104-column addressable array. each pixel can be selected when the page and column addresses are specified. the 89 rows are divided into 11 pages of 8 lines and the 12th page with a single line (db0 only). data is read from or written to the 8 lines of each page directly t hrough db0 to db7. the display data of db0 to db7 from the microprocessor correspond to the lcd common lines as shown in figure 6 . the microprocessor can read from and write to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. com0 - - com1 - - com2 - - com3 - - com4 - - db0 0 0 1 - - 0 db1 1 0 0 - - 1 db2 0 1 1 - - 0 db3 1 0 1 - - 0 db4 0 0 0 - - 1 d isplay data ram lcd display figure 6 . ram-to-lcd data transfer page address circuit this circuit is for providing a p age a ddress to display data ram shown in figure 8 . it incorporates 4-bit p age a ddress register changed by only the "set page" instruction. page a ddress 1 1 (db3 , db1 and db0 are " h " , db2 is "l") is a special ram area for the icons and display data db0 is only valid. line address circuit this circuit assigns ddram a l ine a ddress corresponding to the first line (com0) of the display. therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip ram as shown in figure 8 & figure 9 . it incorporates 7-bit l ine a ddress register changed by only the i nitial d isplay l ine instruction and 7-bit counter circuit. at the beginning of each lcd frame, the contents of register are copied to the line counter which is increased by cl signal and generates the l ine ad dress for transferring the 104-bit ram data to the display data latch circuit. however, display data of icons are not scrolled because the mpu can not access l ine a ddress of icons.
104 seg / 81 com driver & controller for stn lcd S6B0718 16 column address circuit column address circuit has a 7-bit preset counter that provides column address to the display data ram as shown in figure 8 . when set column address msb / lsb instruction is issued, 7-bit [y6:y0] is updated. and, since this address is increased by 1 each a r ead or w rite d ata instruction, microprocessor can access the display data continuously. however, the counter is not incremented and locked if a non-existing address above 67h. it is unlocked if a c olumn a ddress is set again by set column address msb / lsb instruction. and t he c olumn a ddress counter is independent of page address register. adc select instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing adc select instruction. refer to the following figure 7 . seg output seg 0 seg 1 seg 2 seg 3 ... ... seg 100 seg 101 seg 102 seg 103 column address [y6:y0] 00h 01h 02h 03h ... ... 64h 65h 66h 67h display data 1 0 1 0 1 1 0 0 lcd panel display ( adc = 0 ) ... ... lcd panel display ( adc = 1 ) ... ... figure 7 . the relationship between the column address and the segment outputs segment control circuit this circuit controls the display data by the display on / off, reverse display on / off and entire display on / off instructions without changing the data in the display data ram.
S6B0718 104 seg / 81 com driver & controller for stn lcd 17 page 0 page 2 page 1 page 3 page 11 line address com output page address db3 db0 db1 db2 data seg103 seg102 seg1 seg0 seg101 seg100 seg99 seg98 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh com0 com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com29 com28 com27 com26 com25 com23 com24 com22 com21 com30 com59 com58 com57 com31 com60 com69 com68 com67 com66 com65 com63 com64 com62 com61 com70 com79 com78 com77 com76 com75 com73 com74 com72 com71 coms initial line register = 00h 40h 41h 42h 43h 44h 4ch 4bh 4ah 49h 48h 47h 46h 45h 4dh 4eh 4fh 50h 51h 52h 53h 57h 56h 55h 54h 1/73 duty 1/81 duty when initial line address = 00h 38h 39h 3ah 3bh 3ch 3fh 3eh 3dh 00 - - - - - 01 02 03 04 05 62 63 64 65 66 67 00 - - - - - 01 02 03 04 05 62 63 64 65 66 67 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 com56 page10 page9 page8 page7 figure 8 . display data ram map (initial l ine a ddress = 00h)
104 seg / 81 com driver & controller for stn lcd S6B0718 18 page 0 page 2 page 1 page 3 page9 page11 page 11 line address com output page address db3 db0 db1 db2 data seg103 seg102 seg1 seg0 seg101 seg100 seg99 seg98 seg2 seg3 seg4 seg5 - - - - - adc=1 adc=0 column address lcd output db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 db5 db4 db3 db2 db1 db0 00h 08h 07h 06h 05h 04h 03h 02h 01h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 18h 17h 16h 15h 14h 13h 12h 11h 19h 1ah 1bh 1ch 1dh 1eh 1fh com0 com9 com8 com7 com6 com5 com3 com4 com2 com1 com10 com19 com18 com17 com16 com15 com13 com14 com12 com11 com20 com23 com22 com21 com59 com58 com57 com60 com69 com68 com67 com66 com65 com63 com64 com62 com61 com70 com79 com78 com77 com76 com75 com73 com74 com72 com71 coms initial line register = 08h page 8 page 7 page 9 page 10 40h 41h 42h 43h 44h 4ch 4bh 4ah 49h 48h 47h 46h 45h 4dh 4eh 4fh 50h 51h 52h 53h 57h 56h 55h 54h 1/73 duty 1/81 duty when initial line address = 08h 38h 39h 3ah 3bh 3ch 3fh 3eh 3dh 00 - - - - - 01 02 03 04 05 62 63 64 65 66 67 00 - - - - - 01 02 03 04 05 62 63 64 65 66 67 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 com55 com51 com50 com49 com48 com47 com52 com53 com54 figure 9 . display data ram map (initial l ine a ddress = 08h)
S6B0718 104 seg / 81 com driver & controller for stn lcd 19 lcd display circuits oscillator this is completely on-chip o scillator and its frequency is nearly independent of v dd . this o scillator signal is used in the voltage converter and display timing generation circuit. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl, generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock (cl) and the display data latch circuit latches the 104- bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame signal or the line signal changes the m by setting internal instruction. driving waveform and internal timing signal are shown in figure 10 . in a multi ple chip configuration , the slave chip requires the cl, m and sync signals from the master. table 11 shows the cl, sync, and m status. table 11 . master and slave timing signal status operation mode oscillator cl sync m master on (internal clock used) output output output slave off (external clock used) input input input
104 seg / 81 com driver & controller for stn lcd S6B0718 20 fr m 80 81 1 2 3 4 5 6 7 8 9 10 11 12 74 75 76 77 78 79 80 81 1 2 3 4 5 6 cl com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 10 . 2- f rame ac driving waveform ( d uty r atio = 1/81) fr m 80 81 1 2 3 4 5 6 7 8 9 10 11 12 74 75 76 77 78 79 80 81 1 2 3 4 5 6 cl com0 v0 v1 v2 v3 v4 vss com1 v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss segn figure 11 . n-line inversion driving waveform (n = 5, duty ratio = 1/81)
S6B0718 104 seg / 81 com driver & controller for stn lcd 21 lcd driver circuit 8 1 -channel common driver and 104-channel segment driver configure this driver circuit. this lcd panel driver voltage depends on the combination of display data and m signal. com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 seg2 seg1 seg0 com2 com0 com1 m v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss v0 v1 v2 v3 v4 vss vdd vss figure 12 . segment and common timing
104 seg / 81 com driver & controller for stn lcd S6B0718 22 partial display on lcd the S6B0718 realizes the p artial d isplay function on lcd with low-duty driving for saving power consumption and showing the various display duty. to show the various display duty on lcd, lcd driving duty and bias are programmable via the instruction. and, built-in power supply circuits are controlled by the instruction for adjusting the lcd d riving voltages -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 13 . reference example for partial display (display duty = 25) -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 14 . partial display (partial display duty = 9, initial com0 = 0)
S6B0718 104 seg / 81 com driver & controller for stn lcd 23 -- coms -- com0 -- com1 -- com2 -- com3 -- com4 -- com5 -- com6 -- com7 -- com8 -- com9 -- com10 -- com11 -- com12 -- com13 -- com14 -- com15 -- com16 -- com17 -- com18 -- com19 -- com20 -- com21 -- com22 -- com23 figure 15 . moving display (partial display duty = 9, initial com0 = 8 )
104 seg / 81 com driver & controller for stn lcd S6B0718 24 power supply circuits the p ower s upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low-power consumption and the fewest components. there are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. they are valid only in master operation and controlled by p ower c ontrol instruction. for details, refers to "instruction description". table 12 shows the referenced combinations in using p ower s upply circuits. table 12 . recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vout v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on open open open only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input open open only the voltage follower circuits are used 0 0 1 off off on external input open open only the external power supply circuits are used 0 0 0 off off off open external input external input
S6B0718 104 seg / 81 com driver & controller for stn lcd 25 voltage converter circuits these circuits boost up the electric potential between vci and vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from vout pin. it is possible to select the lower boosting level in any boosting circuit by ? set dc-dc step-up ? instruction. when the higher level is selected by instruction, vout voltage is not valid. [c1 = 1.0 to 4.7 m f] vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + vout = 3 x vci c1 - + c1 - + - vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - vout = 4 x vci figure 16 . three times boosting circuit figure 17 . four times boosting circuit vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - vss vout c5+ c3+ c1- c1+ c2+ c2 - c4+ vss vci c1 - + c1 - + c1 - + - c1 - + - c1 - + - c1 - + c1 - + vout = 5 x vci vout = 6 x vci c1 - + - figure 18 . five times boosting circuit figure 19 . six times boosting circuit
104 seg / 81 com driver & controller for stn lcd S6B0718 26 voltage regulator circuits the function of the internal v oltage r egulator circuits is to determine liquid crystal operating voltage, v0, by adjusting resistors, ra and rb, within the range of |v0| < |vout|. because vout is the operating voltage of operational-amplifier circuits shown in figure 20 , it is necessary to be applied internally or externally. for the eq. 1, we determine v0 by ra, rb and v ev . the ra and rb are connected internally or externally by intrs pin. and v ev called the voltage of electronic volume is determined by eq. 2, where the parameter a is the value selected by instruction, "set reference voltage register", within the range 0 to 63. v ref voltage at ta= 25 c is shown in table 13 . rb v0 = (1 + ???? ) x v ev [v] ------ (eq. 1) ra (63 - a ) v ev = (1 - ?????? ) x v ref [v] ------ (eq. 2) 200 table 13 . . v ref voltage at ta = 25 c ref temp. coefficient v ref [ v ] 1 -0.05% / c 2.0 0 external input vext v ev gnd ra rb vss vr v0 vout + - figure 20 . internal voltage regulator circuit
S6B0718 104 seg / 81 com driver & controller for stn lcd 27 in case of using internal resistors, ra and rb (intrs = "h ? ) when intrs pin is " h " , resistor ra is connected internally between vr pin and v ss , and rb is connected between v0 and vr. we determine v0 by two instructions, "regulator resistor select" and "set reference voltage". table 14 . internal rb / ra ratio depending on 3-bit data (r2 r1 r0) 3-bit data settings (r2 r1 r0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 + (rb / ra) 2.6 3.4 4.2 5.0 5.8 6.6 7.4 8.3 figure 21 shows v0 voltage measured by adjusting internal regulator register ratio (rb / ra) and 6-bit electronic volume registers for each temperature coefficient at ta = 25 c. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 15.00 0 8 16 24 32 40 48 56 (1, 1, 1) (1, 1, 0) (1, 0, 1) (1, 0, 0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) rb/ ra ratio 63 electr on ic volume resistor v0 voltage [v] figure 21 . electronic volume level (temp. coefficient = -0.05% / c)
104 seg / 81 com driver & controller for stn lcd S6B0718 28 in case of using external resistors, ra and rb (intrs = "l") when intrs pin is " l " , it is necessary to connect external regulator resistor ra between vr and vss, and rb between v0 and vr. example: for the following requirements 1. lcd driver voltage, v0 = 10v 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. maximum current flowing ra, rb = 1 ua from eq. 1 rb 10 = (1 + ??? ) x v ev [v] ------ (eq. 3) ra from eq. 1 (63 - 32) v ev = (1 - ?????? ) x 2.0 = 1.69 [v] ------ (eq. 4) 200 from requirement 3. 10 ????? = 1 [ua] ------ (eq. 5) ra + rb from equations eq. 3, 4 and 5 ra = 1.69 [m w ] rb = 8.31 [m w ] table 15 shows the range of v0 depending on the above requirements. table 15 . the r ange of v0 electronic volume level 0 ....... 32 ....... 63 v0 8.10 ....... 10.00 ....... 11.83 voltage follower circuits vlcd voltage (v0) is resistively divided into four voltage levels (v1, v2, v3 and v4), and those output impedance are converted by the v oltage f ollower for increasing drive capability. table 16 shows the relationship between v1 to v4 level and each duty ratio. table 16 lcd bias v1 v2 v3 v4 remarks 1/n (n-1)/n x v0 (n-1)/n x v0 2/n x v0 1/n x v0 n = 4 to 11
S6B0718 104 seg / 81 com driver & controller for stn lcd 29 referece circuit examples [c1 = 1.0 to 4.7 [ m f], c2 = 0.1 to 0.47 [ m f]] when using internal regulator resistors when not using internal regulator resistors v ss c1 c1 c1 c1 c1 c1 + + + + + v dd ms intrs vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c1 c1 c1 c1 c1 c1 + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss rb ra c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 ms intrs figure 22 . when using a ll lcd power circuits (6-time v/c: o n , v/r: o n , v/f: o n ) when using internal regulator resistors when not using internal regulator resistors v ss + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss + + + + + v dd vout c5+ vr v4 v3 v2 v1 v0 c4+ c2 - c2+ c1+ c1 - c3+ v ss c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 ms intrs ms intrs external power supply external power supply rb ra figure 23 . when using s ome lcd power circuits (v/c: o ff , v/r: o n , v/f: on )
104 seg / 81 com driver & controller for stn lcd S6B0718 30 v ss v dd ms intrs vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr v0 v1 v2 v3 v4 external power supply + + + + + figure 24 . when using o nly voltage follower circuit (v/c: o ff , v/r: o ff , v/f: o n ) v dd ms intrs vout c5+ c3+ c1- c1+ c2+ c2- c4+ vr external power supply v0 v1 v2 v3 v4 figure 25 . when not using a ll lcd power circuits (v/c: o ff , v/r: o ff , v/f: o ff )
S6B0718 104 seg / 81 com driver & controller for stn lcd 31 reset circuit setting resetb to " l " or reset instruction can initialize internal function. when resetb becomes " l " , following procedure is occurred. page address : 0 column address: 0 modify-read: off display on / off: off initial display line: 0 (first) initial com0 register: 0 (com0) partial display duty ratio: 1/81 reverse display on / off: off (normal) entire display on / off: off (normal) power control register (vc, vr, vf) = (0, 0, 0) dc-dc step up: 3 times converter circuit = (0, 0) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register: (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) lcd bias ratio: 1/10 shl select: off (normal) adc select: off (normal) static indicator mode: off static indicator register: (s1, s0) = (0, 0) oscillator status: off power save mode: release when reset instruction is issued, following procedure is occurred. page address: 0 column address: 0 modify-read: off initial display line: 0 (first) regulator resistor select register: (r2, r1, r0) = (0, 0, 0) reference voltage control register (ev5, ev4, ev3, ev2, ev1, ev0) = (1, 0, 0, 0, 0, 0) static indicator mode: off static indicator register: (s1, s0) = (0, 0) other instruction registers : not changed while resetb is " l " or reset instruction is executed, no instruction except read status can be accepted. reset status appears at db4. after db4 becomes " l " , any instruction can be accepted. resetb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resetb is essential before used.
104 seg / 81 com driver & controller for stn lcd S6B0718 32 instruction description table 17 . instruction table : don ? t care instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description read display data 1 1 read data read data from ddram write display data 1 0 write data write data into ddram read status 0 1 busy adc on res 0 0 0 0 read the internal status set page address 0 0 1 0 1 1 p3 p2 p1 p0 set page address set column address msb 0 0 0 0 0 1 0 y6 y5 y4 set column address msb set column address lsb 0 0 0 0 0 0 y3 y2 y1 y0 set column address lsb set modify-read 0 0 1 1 1 0 0 0 0 0 set modify-read mode reset modify-read 0 0 1 1 1 0 1 1 1 0 release modify-read mode display on / off 0 0 1 0 1 0 1 1 1 d d = 0: display off d = 1: display on 0 0 0 1 0 0 0 0 set initial display line register 0 0 s6 s5 s4 s3 s2 s1 s0 2-byte i nstruction to specify the initial display line to realize vertical scrolling 0 0 0 1 0 0 0 1 set initial com0 register 0 0 c6 c5 c4 c3 c2 c1 c0 2-byte i nstruction to specify the initial com0 to realize window scrolling 0 0 0 1 0 0 1 0 set partial display duty ratio 0 0 d6 d5 d4 d3 d2 d1 d0 2-byte i nstruction to set partial display duty ratio reverse display on / off 0 0 1 0 1 0 0 1 1 rev rev = 0: normal display rev = 1: reverse display entire display on / off 0 0 1 0 1 0 0 1 0 eon eon = 0: normal display eon = 1: entire display on
S6B0718 104 seg / 81 com driver & controller for stn lcd 33 table 17. instruction table (continued) instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 description power control 0 0 0 0 1 0 1 vc vr vf control power circuit operation select dc-dc step-up 0 0 0 1 1 0 0 1 dc1 dc0 select the step-up of the internal voltage converter select regulator resistor 0 0 0 0 1 0 0 r2 r1 r0 select internal resistance ratio of the regulator resistor 0 0 1 0 0 0 0 0 0 1 set electronic volume register 0 0 ev5 ev4 ev3 ev2 ev1 ev0 2-byte i nstruction to specify the electronic volume register select lcd bias 0 0 0 1 0 1 0 b2 b1 b0 select lcd bias shl select 0 0 1 1 0 0 shl com bi-directional selection shl = 0: normal direction shl = 1: reverse direction adc select 0 0 1 0 1 0 0 0 0 adc seg bi-directional selection adc = 0: normal direction adc = 1: reverse direction set static indicator mode 0 0 1 0 1 0 1 1 0 sm set static indicator register 0 0 s1 s0 2-byte i nstruction to specify the static indicator mode oscillator on start 0 0 1 0 1 0 1 0 1 1 start the built-in oscillator set power save mode 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode 0 0 1 1 1 0 0 0 0 1 release power save mode reset 0 0 1 1 1 0 0 0 1 0 initialize the internal functions nop 0 0 1 1 1 0 0 0 1 1 no operation test instruction 0 0 1 1 1 1 don't use this instruction.
104 seg / 81 com driver & controller for stn lcd S6B0718 34 read display data 8-bit data from d isplay d ata ram specified by the column address and page address can be read by this instruction. as the column address is incremented by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. a dummy read is required after loading an address into the column address register. display d ata cannot be read through the serial interface. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 1 read data write display data 8-bit data of display data from the microprocessor can be written to the ram location specified by the column address and page address. the column address is incremented by 1 automatically so that the microprocessor can continuously w rite data to the addressed page. rs rw db7 db6 db5 db4 db3 db2 db1 db0 1 0 write data d ata w rite s et co lumn a ddress s et p age address o ptional s tatus c olumn = co lumn +1 n o y es data w rite c ontinue ? d ummy d ata r ead s et c olumn a ddress s et p age a ddress o ptional s tatus c olumn = c olumn +1 n o y es d ata r ead c ontinue ? d ata r ead c olumn = c olumn +1 figure 26 . sequence for writing display data figure 27 . sequence for reading display data
S6B0718 104 seg / 81 com driver & controller for stn lcd 35 read status indicates the internal status of the S6B0718 rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 1 busy adc on res 0 0 0 0 flag description busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0: chip is active, 1: chip is being busy. adc indicates the relationship between ram column address and segment driver. 0: reverse direction (seg103 ? seg0), 1: normal direction (seg0 ? seg103) on indicates display on / off status. 0: display on, 1: display off res indicates the initialization is in progress by resetb signal. 0: chip is active, 1: chip is being reset. set page address sets the p age a ddress of display data ram from the microprocessor into the p age a ddress register. any ram data bit can be accessed when its p age ad dress and column address are specified. along with the column address, the p age a ddress defines the address of the display ram to write or read display data. changing the p age a ddress doesn't effect to the display status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 1 p3 p2 p1 p0 p3 p2 p1 p0 selected page description 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 : : : : : 1 0 0 1 9 1 0 1 0 10 accessible pages for displaying dot-matrix display data 1 0 1 1 11 accessible page for displaying icons 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 not accessible page. do not use these pages.
104 seg / 81 com driver & controller for stn lcd S6B0718 36 set column address sets the c olumn a ddress of display ram from the microprocessor into the column address register. along with the c olumn a ddress, the column address defines the address of the display ram to write or read display data. when the microprocessor reads or writes display data to or from display ram, c olumn a ddresses are automatically incremented. set column address msb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 y6 y5 y4 set column address lsb rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 y3 y2 y1 y0 y6 y5 y4 y3 y2 y1 y0 selected column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 : : : : : : : : : : : : : : : : : : : : : : : : 1 1 0 0 1 0 1 101 1 1 0 0 1 1 0 102 1 1 0 0 1 1 1 103 1 1 0 1 0 0 0 : : : : : : : : : : : : : : : : : : : : : 1 1 1 1 1 1 1 not accessible column do not use these columns.
S6B0718 104 seg / 81 com driver & controller for stn lcd 37 set modify-read this instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. and it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. this mode is canceled by the reset modify-read instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 0 reset modify-read this instruction cancels the modify-read mode, and makes the column address return to its initial value just before the set modify -r ead instruction is started. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 1 1 1 0 set modify- r ead reset modify- r ead set page address data p rocess n o y es change c omplete ? set column address (n) dummy r ead data r ead data w rite return c olumn a ddress (n) figure 28 . sequence for cursor display
104 seg / 81 com driver & controller for stn lcd S6B0718 38 display on / off turns the display on or off rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 1 d d = 1: display on d = 0: display off set initial display line register sets the line address of display ram to determine the initial display line using 2-byte instruction. the ram display data is displayed at the top row (com0) of lcd panel. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s6 s5 s4 s3 s2 s1 s0 s6 s5 s4 s3 s2 s1 s0 selected line address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 0 1 0 1 1 0 86 1 0 1 0 1 1 1 87 1 0 1 1 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction (2- b yte i nstruction for r egister s etting) setting i initial d isplay l ine e nd 1 st i nstruction (2- b yte i nstruction for m ode s etting) setting i nitial d isplay l ine s tart figure 29 . the sequence for setting the initial display line
S6B0718 104 seg / 81 com driver & controller for stn lcd 39 set initial com0 register sets the initial row (com) of the lcd panel using the 2-byte instruction. by using this instruction, it is possible to realize the window moving without the change of display data. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 c6 c5 c4 c3 c2 c1 c0 c6 c5 c4 c3 c2 c1 c0 initial com0 0 0 0 0 0 0 0 com0 0 0 0 0 0 0 1 com1 0 0 0 0 0 1 0 com2 0 0 0 0 0 1 1 com3 : : : : : : : : 1 0 0 1 1 0 0 com76 1 0 0 1 1 0 1 com77 1 0 0 1 1 1 0 com78 1 0 0 1 1 1 1 com79 1 0 1 0 0 0 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction ( i nitial com0 s etting) setting i nitial com0 e nd end 1 st i nstruction ( m ode s etting) setting i nitial com0 s tart figure 30 . sequence for setting the initial com0
104 seg / 81 com driver & controller for stn lcd S6B0718 40 set partial display duty ratio sets the duty ratio within range of 9 to 8 1 to realize partial display by using the 2-byte instruction. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 selected partial duty ratio 0 0 0 0 0 0 0 : : : : : : : 0 0 0 1 0 0 0 no operation 0 0 0 1 0 0 1 1/9 0 0 0 1 0 1 0 1/10 0 0 0 1 0 1 1 1/11 0 0 0 1 1 0 0 1/12 : : : : : : : : 1 0 0 1 1 1 0 1/78 1 0 0 1 1 1 1 1/79 1 0 1 0 0 0 0 1/80 1 0 1 0 0 0 1 1/81 1 0 1 0 0 1 0 : : : : : : : 1 1 1 1 1 1 1 no operation 2 nd i nstruction ( p artial d isplay d uty s etting) setting p artial d isplay e nd 1 st i nstruction ( m ode s etting) setting p artial d isplay s tart figure 31 . sequence for setting partial display
S6B0718 104 seg / 81 com driver & controller for stn lcd 41 reverse display on / off reverses the display status on lcd panel without rewriting the contents of the display data ram. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 1 rev rev ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (reverse) lcd pixel is not illuminated lcd pixel is illuminated entire display on / off forces the whole lcd points to be turned on regardless of the contents of the display data ram. at this time, the contents of the display data ram are held. this instruction has priority over the r everse d isplay on / off instruction. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 1 0 eon eon ram bit data = ? 1 ? ram bit data = ? 0 ? 0 (normal) lcd pixel is illuminated lcd pixel is not illuminated 1 (entire) lcd pixel is illuminated lcd pixel is illuminated power control selects one of eight power circuit functions by using 3-bit register. an external power supply and part of internal power supply functions can be used simultaneously. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 1 vc vr vf vc vr vf status of internal power supply circuits 0 1 internal voltage converter circuit is off internal voltage converter circuit is on 0 1 internal voltage regulator circuit is off internal voltage regulator circuit is on 0 1 internal voltage follower circuit is off internal voltage follower circuit is on
104 seg / 81 com driver & controller for stn lcd S6B0718 42 select dc-dc step-up selects one of 4 dc-dc step-up to reduce the power consumption by this instruction. it is very useful to realize the partial display function. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 0 1 dc1 dc0 dc1 dc0 selected dc-dc converter circuit 0 0 3 times boosting circuit 0 1 4 times boosting circuit 1 0 5 times boosting circuit 1 1 6 times boosting circuit regulator resistor select selects resistance ratio of the internal resistor used in the internal voltage regulator. see voltage regulator section in power supply circuit. refer to the table 15. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 0 r2 r1 r0 r2 r1 r0 [rb / ra] ratio 0 0 0 small 0 0 1 : : : : : 1 1 0 : 1 1 1 large
S6B0718 104 seg / 81 com driver & controller for stn lcd 43 set electronic volume register consists of 2-byte instruction the 1 st instruction sets electronic volume mode, the 2 nd one updates the contents of electronic volume register. after second instruction, electronic volume mode is released. the 1 st instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 0 1 the 2 nd instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 ev5 ev4 ev3 ev2 ev1 ev0 ev5 ev4 ev3 ev2 ev1 ev0 reference voltage ( a ) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd i nstruction for r egister s etting setting e lectronic v olume e nd 1 st i nstruction for m ode s etting setting e lectronic v olume s tart figure 32 . sequence for setting the electronic volume
104 seg / 81 com driver & controller for stn lcd S6B0718 44 select lcd bias selects lcd bias ratio of the voltage required for driving the lcd. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 0 b2 b1 b0 b2 b1 b0 selected lcd bias 0 0 0 1/4 0 0 1 1/5 0 1 0 1/6 0 1 1 1/7 1 0 0 1/8 1 0 1 1/9 1 1 0 1/10 1 1 1 1/11 shl select com output scanning direction is selected by this instruction which determines the lcd driver output status. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 shl shl = 0: normal direction (com0 ? com79) shl = 1: reverse direction (com79 ? com0) adc select changes the relationship between ram column address and segment driver. the direction of segment driver output pins c ould be reversed by software. this makes ic layout flexible in lcd module assembly. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 0 0 0 adc adc = 0: normal direction (seg0 ? seg103) adc = 1: reverse direction (seg103 ? seg0)
S6B0718 104 seg / 81 com driver & controller for stn lcd 45 set static indicator state consists of two bytes instruction. the first byte instruction ( s et static indicator mode) enables the second byte instruction (set static indicator register) to be valid. the first byte sets the s tatic i ndicator on / off. when it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this s tatic i ndicator state is released after setting the data of indicator register. the 1 st instruction: set static indicator mode (on / off) rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 1 0 sm sm = 0: static indicator off sm = 1: static indicator on the 2 nd instruction: set static indicator register rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 s1 s0 s1 s0 status of static indicator output 0 0 off 0 1 on (about 0.5 second blinking) 1 0 on (about 1 second blinking ) 1 1 on (always on) oscillator on start this instruction enables the built-in oscillator circuit. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 1 1 reset this instruction r esets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data ram. this instruction cannot initialize the lcd power supply, which is initialized by the resetb pin. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 0
104 seg / 81 com driver & controller for stn lcd S6B0718 46 power save the S6B0718 enters the power save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. set power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 1 0 1 0 0 p p = 0: standby mode p = 1: sleep mode release power save mode rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 0 1 release standby mode release sleep mode standby mode oscillator circuits: on static driver: enable lcd power supply circuits: off all com / seg output level: vss consumption current < 15 ua sleep mode oscillator circuits: off static driver: disable lcd power supply circuits: off all com / seg output level: vss consumption current < 2 ua set power save mode release power save mode figure 33 . power save routine n op non operation instruction rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 0 0 0 1 1 test instruction this instruction is for testing ic. please do not use it. rs rw db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 1 1
S6B0718 104 seg / 81 com driver & controller for stn lcd 47 referential instruction setup flow: initializing with the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power resetb pin = "h" user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of initialization figure 34 . initializing w ith the built- i n power supply circuits
104 seg / 81 com driver & controller for stn lcd S6B0718 48 referential instruction setup flow: initializing without the built-in power supply circuits user system setup by external pins start of initialization power on (vdd-vss) keeping the resetb pin = "l" waiting for stabilizing the power set power save user application setup by internal instructions [display duty select] [adc select] [shl select] [com0 register select] user lcd power setup by internal instructions [oscillator on] regulator or follower register select [power control] waiting for stabilizing the lcd power levels end of initialization resetb pin = "h" release power save figure 35 . initializing w ithout the built- i n power supply circuits
S6B0718 104 seg / 81 com driver & controller for stn lcd 49 referential instruction setup flow: data displaying end of initialization write display data by instruction [display data write] turn display on / off instruction [display on / off] end of data display display data ram addressing by instruction [initial display line] [set page address] [set column address] figure 36 . data displaying r eferential instruction setup flow: power off optional status power off (vdd-vss) end of power off set power save by instruction figure 37 . power o ff
104 seg / 81 com driver & controller for stn lcd S6B0718 50 referential instruction setup flow: partial duty changing start of partial changing set display off by internal instruction [display on / off] set partial duty by internal instructions [partial display duty ratio select] [initial display line register] [com0 register select] user lcd power setup by internal instructions [dc-dc step-up register select] [regulator resistor select] [electronic volume register select] [lcd bias register select] [power control] waiting for stabilizing the lcd power levels end of partial changing release power save set standby mode by internal instruction [power save mode] write display data & display on by internal instruction [display data write] [display on / off] waiting for discharging the lcd power levels figure 38 . partial duty changing note :1. partial com0 r egister s etting for com h/w half: [ 8 0 ? ( u ser d uty) ] / 2
S6B0718 104 seg / 81 com driver & controller for stn lcd 51 specifications absolute maximum ratings table 18 . absolute maximum ratings (v ss = 0v) parameter symbol rating unit v dd - 0.3 ~ + 7.0 v v 0 , v out + 0.3 ~ + 17 .0 v supply voltage range v 1 , v 2 , v 3 , v 4 + 0.3 ~ v 0 v external reference voltage v ext +0.3 ~ v dd input voltage range v in - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 40 ~ + 85 c storage temperature range t str - 55 ~ + 125 c notes: 1. vdd, v0, vout, v1 to v4, vext and vci are based on v ss = 0v. 2. voltage vout 3 v0 3 v1 3 v2 3 v3 3 v4 3 vss must always be satisfied. 3. if supply voltage exceeds its absolute maximum range, this lsi may be damaged permanently. it is desirable to use this lsi under electrical characteristic conditions during general operation. otherwise, this lsi may malfunction or reduced lsi reliability may result.
104 seg / 81 com driver & controller for stn lcd S6B0718 52 dc characteristics table 19 . dc characteristics (v ss = 0v, v dd = 2.4~ 3,6 v, ta=-40~85 c) item symbol condition min. typ. max. unit pin used operating voltage (1) v dd 2.4 - 3.6 v v dd *1 operating voltage (2) v 0 4.0 - 1 5 .0 v v0, *2 high v ih 0.8v dd - v dd input voltage low v il v ss - 0.2v dd v *3 high v oh i oh = -0.5ma 0.8v dd - v dd output voltage low v ol i ol = 0.5ma v ss - 0.2v dd v *4 input leakage current i il v in = v dd or v ss - 1.0 - + 1.0 m a *3 output leakage current i oz v in = v dd or v ss - 3.0 - + 3.0 m a *5 lcd driver on resistance r on ta = 25 c, v 0 = 8v - 2.0 3.0 k w segn comn *6 frame frequency f fr ta = 25 c 70 85 100 hz fr *7 table 20 . dc characteristics item symbol condition min. typ. max. unit pin used voltage converter circuit output voltage v out 3 / 4 / 5 / 6 voltage conversion (no-load ) 95 99 - % vout voltage regulator circuit operating voltage v out 6.0 - 1 5 .0 v vout voltage follower circuit operating voltage v 0 4.0 - 1 5 .0 v v0 *8 reference voltage v ref ta = 25 c 1.94 2.00 2.06 v *9
S6B0718 104 seg / 81 com driver & controller for stn lcd 53 dynamic current consumption (1) when an external power supply is used. table 21 . dynamic current 1 (external power) (v dd = 3.0v, ta = 25 c) item symbol condition min typ max unit pin used v0-vss = 1 2 .0v, duty = 1/81 (display off) - - 10 m a *10 dynamic current consumption (1) i dd1 v0-vss = 1 2 .0v, duty = 1/81 (display on , checker pattern) - - 15 m a *10 dynamic current consumption (2) when the internal power supply is on table 22 . . dynamic current 2 (internal power) (v dd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used v0 - vss = 1 2 .0v, x 5 boosting, duty = 1/81, normal mode (display off) - - 150 m a *10 dynamic current consumption (2) i dd2 v0 - vss = 1 2 .0v, x 5 boosting, duty = 1/81, normal mode (display on , checker pattern) - - 300 m a * 10 current consumption during power save mode table 23 . power save mode current (v dd = 3.0v, ta = 25 c) item symbol condition min. typ. max. unit pin used sleep mode current i dds1 during sleep - - 2 m a *10 s tandby mode current i dds 2 during s tandby - - 15 m a *10
104 seg / 81 com driver & controller for stn lcd S6B0718 54 table 24 . the relationship between oscillation frequency and frame frequency duty ratio item f cl f osc 1/n on-chip oscillator circuit is used f fr x n f fr x 4 x n (f osc : oscillation frequency, f cl : display clock frequency, f fr : frame frequency, n = 9 to 81) [* remark solves] *1 . though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the mpu. *2 . in case of external power supply is applied. *3 . cs1b, cs2, rs, db0 to db7, e_rd, rw_wr, resetb, ms, c68, ps, intrs, hpmb, ref, cl, m and sync. *4 . db0 to db7, fr, frs, sync, m and cl. *5 . applies when the db0 to db7, sync, m, and cl pins are in high impedance. *6 . resistance value when -0.1[ma] is applied during the on status of the output pin segn or comn. ron [k w ] = d v[v] / 0.1[ma] ( d v : voltage change when -0.1[ma] is applied in the on status.) *7 . see table 24 for the relationship between oscillation frequency and frame frequency. *8 . the voltage regulator circuit adjusts v0 within the voltage follower operating voltage range. *9 . on-chip reference voltage source of the voltage regulator circuit to adjust v0. *10 . applies to the case where the on-chip oscillation circuit is used and no access is made from the mpu. the current consumption, when the built-in power supply circuit is on or off. the current flowing through voltage regulation resistors(rb and ra) is not included. it does not include the current of the lcd panel capacity, wiring capacity, etc.
S6B0718 104 seg / 81 com driver & controller for stn lcd 55 ac characteristics read / write characteristics (8080-series mp) t dh80 t od80 t ds80 t acc80 0.9v dd 0.1v dd t pwlw , t pwlr t cy80 t ah80 t as80 db0 to db7 ( write ) db0 to db7 ( read ) /rd, /wr cs1b rs t pwhw , t pwhr figure 39 . read / write characteristics ( 8080-series mpu) table 25 (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs t as80 t ah80 0 0 - - ns system cycle time t cy80 4 00 - ns pulse width low for write pulse width high for write rw_wr (/wr) t pwlw t pwhw 60 60 - - ns pulse width low for read pulse width high for read e_rd (/rd) t pwlr t pwhr 120 60 - - ns data setup time data hold time t ds 80 t dh80 40 15 - - ns read access time output disable time db0 to db7 t acc80 t od80 cl = 100 pf - 10 140 100 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy80 - tpwlw - tpwhw ) for write, (tr + tf) < (tcy80 - tpwlr - tpwhr ) for read
104 seg / 81 com driver & controller for stn lcd S6B0718 56 read / write characteristics (6800-series microprocessor) t dh68 t od68 t ds68 t acc68 0.1v dd 0.9v dd t ewhw , t ewhr t cy68 t ah68 t as68 db0 to db7 ( write ) db0 to db7 ( read ) e cs1b rs, r/w t ewlw , t ewlr figure 40 . read / write characteristics (6800-series microprocessor) table 26 (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit address setup time address hold time rs rw t as68 t ah68 0 0 - - ns system cycle time t cy68 4 00 - ns enable width high for write enable width low for write e_rd (e) t ewhw t ewlw 60 60 - - ns enable width high for read enable width low for read e_rd (e) t ewhr t ewlr 120 60 - - ns data setup time data hold time t ds68 t dh68 40 15 - - ns read access time output disable time db0 to db7 t acc68 t od68 c l = 100 pf - 10 140 100 ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tcy68 - tewhw - tewlw ) for write, (tr + tf) < (tcy68 - tewhr - tewlr ) for read
S6B0718 104 seg / 81 com driver & controller for stn lcd 57 serial interface characteristics db7 ( sid ) db6 ( sclk ) rs cs1b (cs2 = "h" ) t dhs t dss t whs 0.9v dd 0.1v dd t wls t cys t ahs t ass t chs t css figure 41 table 27 (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit serial clock cycle sclk high pulse width sclk low pulse width db6 (sclk) ts cy ts hw ts lw 250 100 100 - - - ns address setup time address hold time rs t ass t ahs 150 150 - - ns data setup time data hold time db7 (sid) t dss t dhs 100 100 - - ns cs1b setup time cs1b hold time cs1b t css t chs 150 150 - - ns note: *1. the input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
104 seg / 81 com driver & controller for stn lcd S6B0718 58 reset input timing resetb internal status t rw t r reset complete during reset figure 42 table 28 (v dd = 2.4 ~ 3.6 v, ta = -40 ~ +85 c) item signal symbol condition min. max. unit reset low pulse width resetb t rw 1000 - ns reset time - t r - 1000 ns
S6B0718 104 seg / 81 com driver & controller for stn lcd 59 reference applications microprocessor interface db0 to db7 resetb v dd v dd rw e rs cs2 cs1b 6800-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb c68 ps s6b 0718 figure 43 . in case of interfacing with 6800-series (ps = ? h ? , c68 = ? h ? ) db0 to db7 resetb v dd v ss /wr /rd rs cs2 cs1b 8080-series mpu cs1b cs2 rs e_rd rw_wr db0 to db7 resetb c68 ps s6b 0718 figure 44 . in case of interfacing with 8080-series (ps = ? h ? , c68 = ? l ? ) open resetb vss vdd or vss sclk sid rs cs2 cs1b mpu cs1b cs2 rs db7(sid) db6(sclk) resetb db0 to db5 c68 ps s6b 0718 figure 45 . in case of serial interface (ps = ? l ? , c68 = ? h/l ? )
104 seg / 81 com driver & controller for stn lcd S6B0718 60 connections between S6B0718 and lcd panel single chip configurations (1/81 duty) com 39 - com0 coms coms com 79 - com 40 seg 103 seg 102 ? seg1 seg0 s6b 071 8 (bottom view) com 5 1 - com0 coms coms com 10 3 - com 5 2 seg0 seg1 ? seg 102 seg 103 s6b 071 8 (top view) ? a x a ? a x a 80 104 pixels ? a x a ? a x a 80 104 pixels figure 46 . shl = 0, adc = 1 figure 47 . shl = 0, adc = 0 com 40 com 79 coms coms com0 com 39 seg 15 9 seg 15 8 ? seg1 seg0 s6b 071 8 (top view) coms com0 com 39 com 40 com 79 coms seg0 seg1 ? seg 15 8 seg 15 9 s6b 071 8 (bottom view) ? a x a ? a x a 80 104 pixels ? a x a ? a x a 80 1 04 pixels figure 48 . shl = 1, adc = 0 figure 49 . shl = 1, adc = 1
S6B0718 104 seg / 81 com driver & controller for stn lcd 61 mu l ti ple c hip configurations (1/81 duty) com 39 - com0 coms coms com 79 - com 40 seg 103 seg 102 ? seg1 seg0 s6b 071 8 (bottom view) (master) com 39 - com0 coms coms com 79 - com 40 seg 103 seg 102 ? seg1 seg0 s6b0 71 8 (bottom view) (slave) ? a x a ? a x a 80 208 pixels figure 50 . shl = 0, adc = 1 connect the following pins of two chips each other: - display clock pins: cl, m, sync - lcd power pins: v0, v1, v2, v3, v4 ? a x a ? a x a 80 208 pixels com 40 com 79 coms coms com0 com 39 seg0 seg1 ? seg 102 seg 103 s6b 071 8 (bottom view) (master) com 40 com 79 coms coms com0 com 39 seg0 seg1 ? seg 102 seg 103 s6b 071 8 (bottom view) (slave) figure 51 . shl = 1, adc = 0 connect the following pins of two chips each other: - display clock pins: cl, m, sync - lcd power pins: v0, v1, v2, v3, v4

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